| 张长春,施思,王志功,唐路,黄继伟,郭宇峰.集成时钟产生功能的0.18μm CMOS 10Gb/s复接器的设计[J].高技术通讯(中文),2012,22(5):523~530 |
| 集成时钟产生功能的0.18μm CMOS 10Gb/s复接器的设计 |
| Design of a 10 Gb/s 0.18μm CMOS multiplexer with the integrated clock generation circuit |
| 修订日期：2010-12-18 |
| DOI： |
| 中文关键词: 复接器(MUX)， 时钟提取， 鉴频鉴相器， 压控振荡器， 脉宽失真 |
| 英文关键词: multiplexer (MUX), clock extraction, phase/frequency detector, voltage controlled oscillator，pulse width distortion |
| 基金项目:863计划（2007AA01Z2a5），国家自然科学基金（61076073，60806027）和高等学校博士学科点专项科研基金（20090092120012）资助项目 |
| 作者 | 单位 | | 张长春 | 东南大学射频与光电集成电路研究所；南京邮电大学功率与射频微电子研究中心 | | 施思 | 东南大学射频与光电集成电路研究所 | | 王志功 | 东南大学射频与光电集成电路研究所 | | 唐路 | 东南大学射频与光电集成电路研究所 | | 黄继伟 | 东南大学射频与光电集成电路研究所 | | 郭宇峰 | 东南大学射频与光电集成电路研究所；南京邮电大学功率与射频微电子研究中心 |
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| 中文摘要: |
| 针对传统的复接器(MUX)因没有集成时钟电路而限制了其集成度及应用的问题研究了复接器与时钟电路的集成，并采用中芯国际（SMIC）0.18μm 互补金属氧化物半导体（CMOS）工艺设计并实现了一个片内集成时钟产生功能的10Gb/s半速率2∶1 MUX电路。整个电路由5Gb/s时钟提取电路(CEC)和10Gb/s半速率2∶1 MUX电路构成。 CEC从一路输入数据中提取出5GHz时钟提供给MUX电路。 CEC由鉴频鉴相器(PFD)、电压/电流转换电路、环路滤波器及压控振荡器(VCO)构成。Pottbcker |
| 英文摘要: |
| Considering that, conventionally, a clock function block is not integrated with a multiplexer (MUX), which brings restrictions to MUX’s integration and application, the research on integrating the clock circuit with a multiplexer was performed, and a 10 Gb/s half rate 2∶1 MUX with the integrated clock generation circuit was designed and fabricated in the SMIC 0.18μm CMOS process. The whole circuit consists of a 5Gb/s clock extraction circuit (CEC) and a 10Gb/s half rate 2∶1 MUX. The CEC extracts a 5GHz clock from one of two input data, and then provides the MUX with it. The CEC comprises a phase/frequency detector (PFD), a voltage/current converter (V/I), a loop filter (LF), and a voltage controlled oscillator (VCO). A Pottbcker PFD can not only enlarge the pull in range of the loop, but also tolerate up to ±45° phase error deviating from ideal inphase/quadrature (I/Q) clocks, so a 3 stage ring VCO can be employed. The measuremental results show that the circuit can work without any external component, reference clock, or manual tuning. The chip area is 670μm×760μm. Under a 1.8V supply, it has the power consumption of 180mW, in which, only 60% is used by the core blocks. |
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