| 张立国,雷璇瑞,金梅,吴文哲,宋炳豪.基于图像处理的电路板缺陷检测系统设计[J].高技术通讯(中文),2024,34(2):209~217 |
| 基于图像处理的电路板缺陷检测系统设计 |
| Design of circuit board defect detection system based on image processing |
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| DOI：10. 3772/ j. issn. 1002-0470. 2024. 02. 010 |
| 中文关键词: 图像处理； 缺陷检测； 去除丝印； 模板匹配； 现场可编程门阵列（FPGA） |
| 英文关键词: image processing, defect detection, removing silk-screen, template matching, field programmable gate array (FPGA) |
| 基金项目: |
| 作者 | 单位 | | 张立国 | （燕山大学电气工程学院秦皇岛 066000） | | 雷璇瑞 | | | 金梅 | | | 吴文哲 | | | 宋炳豪 | |
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| 中文摘要: |
| 针对传统电路板缺陷检测多为人工检测、速度较慢且成本较高的问题,本文研究设计了一款以图像处理为基础、利用现场可编程门阵列（FPGA）实现对电路板缺陷准确、高速的检测系统。在传统图像增强算法的基础上提出一种针对不同图像信息采用不同感兴趣区间的方法，增强效果显著；为减少电路板上标识字样对匹配算法计算速度的影响,提出一种去除丝印算法，将电路板上多余的标识字样取消，减少图像匹配的计算量，加快检测的速度;在传统绝对误差和算法(SAD)模板匹配算法的基础上采用去平均值法计算图像信息，减小光照变化带来的影响；将传统2算子Sobel边缘检测扩展到8算子边缘检测，边缘信息更加明显清晰。采用FPGA作为硬件平台，在Vivado开发环境下实现Verilog HDL硬件逻辑语言，下载到FPGA中实现。实验结果表明，系统的平均检测精度为98.53%，检测单张电路板的时间为8.204s。本系统设计在检测精度和速度上都有明显提升，且造价成本低。 |
| 英文摘要: |
| Aiming at the problems that the traditional circuit board defect detection features low speed and high cost due to manual detection is, this paper investigates and designs a precise and efficient circuit board defect detection system utilizing image processing techniques implemented on field programmable gate array (FPGA). Through using different interest intervals for different image information on the basis of traditional image enhancement algorithms, the method yields notable improvements in image enhancement. In order to reduce the impact of logo characters on the circuit board’s computational efficiency for the matching algorithm, a silkscreen removal technology is used to eliminate the superfluous logo characters on the circuit board to decrease the computational load of image matching and enhance the detection speed. Additionally, adopting the de-averaging method based on the traditional sum of absolute differences (SAD) template matching algorithm to calculate image information to alleviate the impact of lighting variations on the overall performance. The traditional 2-operator Sobel edge detection is extended to 8-operator edge detection, resulting in enhanced clarity and prominence of edge information. Using FPGA as the hardware plat-form, Verilog HDL hardware logic language is implemented in Vivado development environment and subsequently deployed onto the FPGA. The experimental results demonstrate that the system attains an average detection accuracy of 98.53%, and its detection time of single circuit board is 8.204s. Its system design provides substantial enhancements in both detection accuracy and speed, while maintaining a cost-effective research approach. |
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