| 宋鹏皓,王剑.针对流多处理器访存资源的动态重分配架构[J].高技术通讯(中文),2026,36(5):467~477 |
| 针对流多处理器访存资源的动态重分配架构 |
| The dynamic memory resource redistribution architecture for streaming multiprocessors |
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| DOI：10. 3772 / j. issn. 1002 - 0470. 2026. 05. 003 |
| 中文关键词: 通用图形处理器； 流多处理器； 访存调度； 动态资源分配； 线程级并行 |
| 英文关键词: general-purpose graphics processing unit, streaming multiprocessor, memory access scheduling, dynamic resource redistribution, thread-level parallelism |
| 基金项目: |
| 作者 | 单位 | | 宋鹏皓 | （计算机体系结构国家重点实验室（中国科学院计算技术研究所）北京 100190）
（中国科学院大学北京 100049） | | 王剑 | |
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| 摘要点击次数: 19 |
| 全文下载次数: 11 |
| 中文摘要: |
| 通用图形处理器作为并行处理领域最重要的硬件范式，其执行性能不仅依赖于计算资源的数量，更与访存效率息息相关。作为通用图形处理器的核心模块，流多处理器在最新设计中均采用了同构子核的分离式结构，这虽然有效降低了功耗和面积的开销，但同时也带来了新的访存调度需求。本文测试了不同子核的访存阻塞比例，同时研究了访存延迟在一级数据缓存中的主要成因。分析结果显示子核同时阻塞现象具有显著的普遍性，此时所有计算资源陷入停滞而被浪费；实验确定了引发请求阻塞的2大核心因素——地址组冲突和缺失队列资源竞争。为了缓解访存阻塞并提高资源利用率，本文提出了针对访存资源的动态重分配架构，该架构包含了重分配状态转换框架与失败队列。前者为所有子核赋予了不同的访存优先级，以减少子核同步前进导致的访存竞争；后者通过在关键位置增加有限资源，有效缓解了缓存中并发请求的竞争压力，从而减少访存阻塞引发的延迟。最终的实验结果显示，相比于基准结构，本文提出的动态重分配架构最高能达到22.03%的性能提升，在测试集上的平均性能提升则有6.28%，同时该架构还能降低3.51%的能量消耗。 |
| 英文摘要: |
| General-purpose graphics processing units (GPGPUs), as the most important hardware paradigm in parallel processing, rely not only on the quantity of computational resources but also critically on memory access efficiency for their execution performance. As the core module of GPGPUs, streaming multiprocessors (SMs) in their latest designs universally adopt the separated architecture of homogeneous sub-cores, which effectively reduces power and area overhead while simultaneously introducing new memory scheduling requirements. This paper examines the memory access blocking ratios across different sub-cores while investigating the primary causes of memory access latency in L1 data caches. Analytical results reveal that simultaneous sub-core blocking exhibits significant prevalence, during which all computational resources remain stagnant and wasted, and experiments identify two core factors causing request blocking——address bank conflicts and miss queue resource contention. To alleviate memory blocking and improve resource utilization, this paper proposes a dynamic redistribution architecture for memory resources, incorporating both a redistribution state transition framework and the fail queues: the former assigns different memory access priorities to all sub-cores to reduce memory competition caused by synchronous advancement; the latter effectively mitigates contention pressure from concurrent requests in caches by adding limited resources at critical locations, thereby reducing latency induced by memory blocking. Final experimental results demonstrate that compared to the baseline architecture, the proposed dynamic redistribution architecture achieves up to 22.03% performance improvement, with an average performance enhancement of 6.28% across the test set, while simultaneously reducing energy consumption by 3.51%. |
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