| 陈洋* **,石晶林* **,刘攀***,王磊***.面向5G终端基带处理的高量化信噪比FFT加速器设计[J].高技术通讯(中文),2023,33(9):905~915 |
| 面向5G终端基带处理的高量化信噪比FFT加速器设计 |
| A high SQNR FFT accelerator design for 5G terminal baseband processing |
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| DOI：10. 3772/ j. issn. 1002-0470. 2023. 09. 002 |
| 中文关键词: 5G移动通信； 终端基带处理； 快速傅里叶变换（FFT）； 块浮点（BFP） |
| 英文关键词: 5G mobile communication, terminal baseband processing, fast Fourier transform (FFT), block floating point (BFP) |
| 基金项目: |
| 作者 | 单位 | | 陈洋* ** | (*中国科学院计算技术研究所移动计算与新型终端北京市重点实验室北京 100190)
(**中国科学院大学北京 100049)
(***北京中科晶上科技股份有限公司北京 100190) | | 石晶林* ** | | | 刘攀*** | | | 王磊*** | |
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| 中文摘要: |
| 针对第5代移动通信系统（5G）终端基带处理芯片的设计要求，本文提出一种基于新型块浮点（BFP）技术的快速傅里叶变换（FFT）加速器。为了降低FFT计算过程中的量化误差，本文实现了一种逐级迭代、动态调整共享指数的块浮点技术，并在此基础上，引入“银行家舍入规则”处理BFP尾数缩放过程中的舍入误差，进一步提高该加速器的整体精度。此外，为了实现5G基带连续FFT处理需求，本文还实现了一种无地址冲突的顺序访存机制。实验结果表明，该加速器从128点至4096点FFT处理的量化信噪比（SQNR）都超过75dB，比未采用块浮点的方案高8~15dB；与其他较优秀的设计相比，在高点数（2048点、4096点）上也有3dB的优势。本文FFT加速器在TSMC 28nm工艺库下综合显示，总面积为0.193mm2，最高支持600MHz时钟频率，计算4096点FFT平均功耗为16.3mW。 |
| 英文摘要: |
| Aiming at the design requirements of 5G terminal baseband processing chips, a fast Fourier transform (FFT) accelerator based on a new block floating point (BFP) technology is proposed. In order to reduce the quantization error in the FFT calculation process, this paper implements a block floating point technique that iterates step by step and dynamically adjusts the shared exponent. On this basis, the “Banker’s Rounding Rule” is introduced to deal with the rounding error in the BFP mantissa scaling process, which further improves the overall accuracy of the accelerator. In addition, in order to realize the continuous FFT processing requirements of 5G baseband, this paper also implements a sequential memory access mechanism without address conflict. Experimenal results show that the quantized signal to noise ratio (SQNR) of the accelerator from 128 point to 4096 point FFT processing exceeds 75dB, which is 8-15dB higher than that of the scheme without block floating point. There is also a 3dB advantage in high points (2048 points, 4096 points) compared with the better designs. The gate level synthesis under TSMC 28nm technology results show that its silicon area is 0.193mm2, the maximum clock frequency is 600MHz, and the average power consumption of 4096 points FFT is 16.3mW. |
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