| 李小波,唐志敏.X-Debugger：基于FPGA的扫描调试器设计及实现[J].高技术通讯(中文),2024,34(8):824~831 |
| X-Debugger：基于FPGA的扫描调试器设计及实现 |
| X-Debugger：an FPGA based scan debugger design and implementation |
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| DOI：10. 3772 / j. issn. 1002-0470. 2024. 08. 004 |
| 中文关键词: 硅后调试； 现场可编程门阵列(FPGA）； 扫描链； 寄存器回读； 状态重建 |
| 英文关键词: post-silicon debug, field programmable gate array (FPGA), scan chain, registers readback, state replay |
| 基金项目: |
| 作者 | 单位 | | 李小波 | (处理器芯片全国重点实验室(中国科学院计算技术研究所)北京 100190)
(中国科学院大学计算机科学与技术学院北京 100049) | | 唐志敏 | |
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| 中文摘要: |
| 针对芯片硅后调试面临内部信号可观测性差、可控制性弱、内部状态不易恢复重建等问题，本文设计和实现了一款基于现场可编程门阵列(FPGA）的快速扫描调试器X-Debugger。该调试器复用传统可测试设计(DFT)扫描链路逻辑，在芯片的设计阶段插入基于功能模块前导码的扫描控制电路，实现了芯片内部各数字逻辑模块信号100%可见；通过基于FPGA的扫描调试器X-Debugger可以快速完成芯片内部寄存器状态获取和修改，并结合硬件加速器可以完成芯片内部逻辑状态的快速重建，从而形成硅后调试闭环。在某处理器芯片硅后调试实践中的结果表明，对于小于100万触发器的功能模块可以在1s内完成内部状态获取、修改和重建，全芯片通过X-Debugger内部信号获取和重建小于1min，极大提高了该处理器芯片的硅后调试效率。 |
| 英文摘要: |
| Chip post silicon debugging faces challenges such as poor internal observability, weak controllability, and difficult internal state replay. This paper designs and implements a field programmable gate array (FPGA) based scan debugger X-Debugger which improves the debug efficiency dramatically. By reusing origin design for test (DFT) scan chain logic, inserting a scan control circuit based on functional module preamble during the chip design phase, the digital logic signals inside the chip are 100% visible. The scan debugger based on FPGA can quickly complete the acquisition and modification of the internal register state of the chip, and complete the replay of the internal logic state of the chip through the emulator rapidly, thus forming a debugging closed loop. The post silicon debugging practice of a processor chip shows that the function module with less than one million registers can complete the internal state acquisition and replay in 1 s, and the whole chip’s internal state can be acquired and replayed in less than 1 min by X-Debugger, which greatly improves the post silicon debugging efficiency of the processor chip. |
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