A TSE based design for MMSE and QRD of MIMO systems based on ASIP

FENG Xuelin (冯雪林)* ** ***; SHI Jinglin*; CHEN Yang*; FU Yanlu***; ZHANG Qineng*; XIAO Feng***

文章摘要

FENG Xuelin (冯雪林)* ** ***,SHI Jinglin*,CHEN Yang*,FU Yanlu***,ZHANG Qineng*,XIAO Feng***.[J].高技术通讯(英文),2023,29(2):166~173

A TSE based design for MMSE and QRD of MIMO systems based on ASIP

DOI：10. 3772/ j. issn. 1006-6748. 2023. 02. 007

中文关键词:

英文关键词: multi input and multi output (MIMO), minimum mean square error (MMSE), QR decomposition (QRD), Taylor series expansion (TSE), application specific instruction set processor (ASIP), instruction set architecture (ISA), single instruction multiple data (SIMD), very long instruction word (VLIW)

基金项目:

Author Name	Affiliation
FENG Xuelin (冯雪林)* *	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)
SHI Jinglin*	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)
CHEN Yang*	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)
FU Yanlu***	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)
ZHANG Qineng*	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)
XIAO Feng***	(* Beijing Key Laboratory of Mobile Computing and Pervasive Device, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080， P.R.China) ( School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049， PRChina) (* Beijing Sylincom Technology Co., Ltd., Beijing 100190， PRChina)

Hits: 540

Download times: 691

中文摘要:

英文摘要:

A Taylor series expansion (TSE) based design for minimum mean square error (MMSE) and QR decomposition (QRD) of multi input and multi output (MIMO) systems is proposed based on application specific instruction set processor (ASIP), which uses TSE algorithm instead of resource consuming reciprocal and reciprocal square root (RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture (ISA) and the allocation of data paths in single instruction multiple data very long instruction word (SIMD VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate area efficiency comparable with ASIC implementations.

View Full Text View/Add Comment Download reader