| DENG Junyong (邓军勇),KANG Yuchun,YE Zekun,ZHU Yun,JIA Yanting.[J].高技术通讯(英文),2025,31(2):105~117 |
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| ParaGraph: a parallel graph computing accelerator based on software-hardware collaboration |
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| DOI：10. 3772 / j. issn. 1006-6748. 2025. 02. 001 |
| 中文关键词: |
| 英文关键词: graph computing, software-hardware co-design, reduced instruction set computing-five (RISC-V), parallel accelerator |
| 基金项目: |
| Author Name | Affiliation | | DENG Junyong (邓军勇) | (School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P. R. China) | | KANG Yuchun | | | YE Zekun | | | ZHU Yun | | | JIA Yanting | |
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| 中文摘要: |
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| 英文摘要: |
| Graph computing has become pervasive in many applications due to its capacity to represent complex relationships among different objects in the big data era. However, general-purpose architectures are computationally inefficient for graph algorithms, and dedicated architectures can provide high efficiency, but lack flexibility. To address these challenges, this paper proposes ParaGraph, a reduced instruction set computing-five (RISC-V)-based software-hardware co-designed graph computing accelerator that can process graph algorithms in parallel, and also establishes a performance evaluation model to assess the efficiency of co-acceleration. ParaGraph handles parallel processing of typical graph algorithms on the hardware side, while performing overall functional control on the software side with custom designed instructions. ParaGraph is verified on the XCVU440 field-programmable gate array ( FPGA) board with E203, a RISC-V processor. Compared with current mainstream graph computing accelerators, ParaGraph consumes 7. 94% less block RAM (BRAM) resources than ThunderGP. Its power consumption is reduced by 86. 90% , 24. 90% , and 76. 38% compared with ThunderGP, HitGraph, and GraphS, respectively. The power efficiency of connected components (CC) and degree centrality (DC) algorithms is improved by an average of 6. 50 times over ThunderGP, 2. 51 times over HitGraph, and 3. 99 times over GraphS. The software-hardware co-design acceleration performance indicators H/ W. Cap for CC and DC are 13. 02 and 14. 02,respectively. |
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