| Tang Lu (唐路),Wang Zhigong,Qiu Yinghua,Xu Jian.[J].高技术通讯(英文),2012,18(3):263~266 |
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| Low phase noise millimeter wave monolithic integrated phase locked-loop |
| Revised:May 10, 2010 |
| DOI：10.3772/j.issn.1006-6748.2012.03.008 |
| 中文关键词: |
| 英文关键词: phase locked loop (PLL), voltage-controlled oscillator (VCO), coplanar waveguides (CPWs), GaAs |
| 基金项目: |
| Author Name | Affiliation | | Tang Lu (唐路) | | | Wang Zhigong | | | Qiu Yinghua | | | Xu Jian | |
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| 中文摘要: |
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| 英文摘要: |
| A Monolithic integrated phase locked-loop (PLL) with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the millimeter-wave band. The on-chip high-Q coplanar waveguides (CPWs) are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL’s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2μm GaAs pseudomorphic high electron mobility transistor (PHEMT) process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean square (RMS) jitter of 1.68ps. |
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