| Chen Yingmei (陈莹梅),Chen Xuehui,Yi Lvfan,Wen Guanguo.[J].高技术通讯(英文),2014,20(2):140~145 |
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| Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS |
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| DOI：10.3772/j.issn.1006-6748.2014.02.005 |
| 中文关键词: |
| 英文关键词: Verilog-HDL, behavioral level model (BLM), phase locked loops(PLL), clock and data recovery (CDR) |
| 基金项目: |
| Author Name | Affiliation | | Chen Yingmei (陈莹梅) | | | Chen Xuehui | | | Yi Lvfan | | | Wen Guanguo | |
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| 中文摘要: |
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| 英文摘要: |
| Phase locked loop (PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant. The behavioral level model (BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper, and the design of PLL based clock and data recovery (CDR) circuit aided with jitter attenuation PLL for SerDes application is also presented. The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop. To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network (ITU-T OTN), an additional jitter attenuation PLL is used. Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17ps and 2.3ps respectively. The core of the whole chip consumes 72mA current from a 1.0V supply. |
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