| Yu Yong (于涌)* ** ***,Zhi Tian*,Zhou Shengyuan***.[J].高技术通讯(英文),2021,27(1):62~67 |
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| LACC: a hardware and software co-design accelerator for deep neural networks |
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| DOI：10.3772/j.issn.1006-6748.2021.01.008 |
| 中文关键词: |
| 英文关键词: deep neural network(DNN), domain specific accelerator, domain specific data type |
| 基金项目: |
| Author Name | Affiliation | | Yu Yong (于涌)* ** *** | (*State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, P.R.China)
(**School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, P.R.China)
(***Cambricon Technologies Ltd, Beijing 100190, P.R.China) | | Zhi Tian* | (*State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, P.R.China) | | Zhou Shengyuan*** | (***Cambricon Technologies Ltd, Beijing 100190, P.R.China) |
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| 中文摘要: |
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| 英文摘要: |
| With the increasing of data size and model size, deep neural networks (DNNs) show outstanding performance in many artificial intelligence (AI) applications. But the big model size makes it a challenge for high-performance and low-power running DNN on processors, such as central processing unit (CPU), graphics processing unit (GPU), and tensor processing unit (TPU). This paper proposes a LOGNN data representation of 8 bits and a hardware and software co-design deep neural network accelerator LACC to meet the challenge. LOGNN data representation replaces multiply operations to add and shift operations in running DNN. LACC accelerator achieves higher efficiency than the state-of-the-art DNN accelerators by domain specific arithmetic computing units. Finally, LACC speeds up the performance per watt by 1.5 times, compared to the state-of-the-art DNN accelerators on average. |
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